ChipletOS · Chip packaging · for a technical reader
The capacitance flat models leave out: the lab’s exact wording
The lab’s own sentences and figures for this result, word for word, in its working terms, with its limits in plain words where the lab’s text cannot be reprinted. The plain account is on the result’s page; it says the same things in plain words.
The lab’s plain-English sentence
The lab built its own three-dimensional electrical solver, checked it first against textbook shapes whose answers are known exactly … about 40% of its charge-storing capacity (capacitance) sits at its two ends, a share that the lab's flat, two-dimensional models leave out by design
- that flat models omit end effects is textbook
- but the corrected number is the 3-D solver's own answer, costing one 3-D solve per layout, and FastCap's own resolution (about 0.5%) is as large as that worst error
- Whether the omission changes any ratio the lab's models actually certify is untested
Agreement with FastCap, an outside 3-D solver run on the lab’s own mesh, in the lab’s words
an independent FastCap N=8 cross-check at 0.80% diagonal / 1.04% dominant off-diagonal
The limit to read first, in the lab’s words
for one idealised vertical metal connection — a bare cylinder in a uniform insulator at one standard size, without the pads and metal planes a real package via ends in
The share at the two ends, in the lab’s words
Roughly 40% of a finite via's driven-pair capacitance is 3-D end-effect
Against FastCap, on fresh layouts drawn from a seed the lab calls pre-registered
0.498% (max) and 0.308% (median) of FastCap on 86 pairs of 12 fresh layouts drawn from a pre-registered seed, against a 42.794% median error uncorrected
Claim
Roughly 40% of a finite via's driven-pair capacitance is 3-D end-effect that a 2-D per-unit-length model structurally omits — measured with our own 3-D solver, validated against exact references before use. Applied as a blocking correction to the 2-D spectral pair solver, it brings that solver within 0.498% (max) and 0.308% (median) of FastCap on 86 pairs of 12 fresh layouts drawn from a pre-registered seed, against a 42.794% median error uncorrected.
[Plain gloss of the claim: the end share is measured for one bare cylinder driven as one of a pair. The corrected solver’s agreement with FastCap is on twelve layouts the lab drew after writing down its bars, with FastCap run on the lab’s own mesh, whose own refinement moves its answer by about as much as the corrected solver’s worst error. The correction costs one three-dimensional solve per layout.]
Limits
[The lab’s limits in plain words, without one sentence of the lab’s own rhetoric. Its solver was first checked against shapes with exact answers, and against FastCap, an outside solver the lab ran itself, at the size the lab labels N=8. The correction used is the measured end term, one three-dimensional solve per layout; a learned estimate rides along as a note only. FastCap’s own change under a finer mesh is about as large as the corrected solver’s worst error. The bars were set after a probe of three shapes, and the twelve layouts drawn after.]
More
- The plain account of this result: the problem, what was shown, what it means for a buyer, who we expect would buy, why now, why you can trust the check, and what it does not show yet.
- This result’s file, the source of every sentence above.