ChipletOS · Chip packaging
The capacitance flat models leave out
The lab’s own three-dimensional solver measured how much of one simplified chip-package connection’s capacitance (its charge-storing capacity) flat, two-dimensional models leave out.
Who did this. The lab’s AI agents did the research and engineering. Nick Harris, founder. CTO of VivaMed BioPharma; co-founder of MedSim.ai, FastRead.io and Formulai. The lab’s track record.
What we showed
of one simplified connection’s capacitance (its charge-storing capacity), measured with the connection driven as one of a pair, sits at its two ends, which flat, two-dimensional models leave out. The lab’s own solver was checked first against shapes with exact answers, then against FastCap, an outside solver run on the lab’s own mesh of the shape.
- Limit.
- One bare cylinder at one standard size, without the pads and metal planes a real package connection ends in. That flat models miss the ends is well known; whether the missing share changes any figure the lab’s own models sign off on has not been tested.
The problem
Chip-package models often treat each vertical connection as an infinitely long flat cross-section, which leaves out the charge stored at its two ends. That flat models leave out the ends is well known, and open three-dimensional tools such as FastCap can already size it.
What it means for a buyer
If you design chip packages or sell the software that models them: a flat model of a vertical connection misses the charge stored at its two ends by construction. The lab built its own three-dimensional solver to measure that share and checked it against shapes with exact answers and against FastCap, an outside solver run on the lab’s own mesh. What this gives a buyer today is a measured size for what a flat model leaves out on one simplified connection, not yet a correction shown to matter on a real package.
Who we expect would buy
Teams we expect would care (no customer or pilot yet): chip-package and glass or silicon interposer design teams, and the extraction-tool vendors that serve them.
Why now
Chiplet packages are going vertical: the UCIe chiplet-interconnect standard now covers stacked, three-dimensional packaging, with bonded connections spaced as little as a micron apart (report). The closer those vertical connections sit, the more a package team depends on a coupling model its reviewers can trust.
Why you can trust the check
The lab’s solver was checked against shapes with exact answers and against FastCap, an outside solver, run on the lab’s own mesh. No automated check in the lab’s code recomputes the headline share on each run, so treat it as a measurement reported once.
No outside firm has audited it. How this result’s check works, step by step.
What this does not show yet
- It is measured for one simplified connection: a bare cylinder in a uniform insulator at one standard size, without the pads and metal planes a real package connection ends in.
- The share is of the capacitance when the connection is driven as one of a pair (the lab’s “driven-pair” capacitance).
- That flat models miss the ends is well known. Whether the missing share changes any figure the lab’s own models sign off on has not been tested.
- FastCap ran on the lab’s own mesh of the shape (the grid of small patches the shape is split into). FastCap’s own answer changes, when that mesh is made finer, by about as much as the two solvers differ from each other. So the mesh alone could explain the difference, and closer agreement than that cannot be claimed.
- No automated check in the lab’s code recomputes this result’s headline share, so treat that figure as a measurement reported once, not one re-checked on every run.
- The lab uses the measured end share as a correction in one of its two-dimensional solvers only, checked for layouts up to the size the lab labels N=8. It is not yet built into the lab’s sign-off certificates, and the lab’s other two-dimensional solvers still leave the ends out.
Prior work
Named in the lab’s prior-art search for this result, and credited here.
- Charge density on thin straight wire, revisited, J. D. Jackson, American Journal of Physics 68, 789, 2000
- Electrostatics of a finite-thickness conducting cylindrical shell: coupled elliptic-kernel integral equations, J. Ricardo de Sousa, arXiv 2601.00858, 2025
- A Direct Solver for the Rapid Solution of Boundary Integral Equations on Axisymmetric Surfaces in Three Dimensions, Patrick M. Young, Per-Gunnar Martinsson, arXiv 1002.2001, 2010
- Capacitance of a Cube and a Hollow Cylinder, Haiyong Gu, Liyuan Huang, Peide Yang, Tianshu Luo, arXiv 2505.13148, 2025
The exact wording, for a technical reader
The lab’s own sentences and figures for this result, word for word, its limits in plain words where the lab’s text cannot be reprinted: The capacitance flat models leave out, exact wording.
Check it yourself
- This result’s file: every sentence and figure on this page that is the lab’s own, copied from its current record at the commit the file names.
- The lab’s result file, copied from its codebase at the commit it names.
- The file that counts which figures the lab’s automated checks read: this result’s headline share is not among them.
- ChipletOS, the company that carries this result.
Related results across the group
- This result on chipletos.com, ChipletOS’s own site.
- A fast coupling model, graded by outside solvers (ChipletOS, chip packaging)
- Checked brightness ranges for chip prints (ChipletOS, chip printing)
- Pair-by-pair coupling estimates overstate the worst case, in a model (ChipletOS, chip packaging)
- Signing off some tiles near a chip-mask edit, in simulation (ChipletOS, chip printing)
- A near-constant-size sign-off record for a photomask (ChipletOS, chip printing)