ChipletOS · Chip packaging
Pair-by-pair coupling estimates overstate the worst case, in a model
A proof, over every layout in one narrow family in a simplified model, that adding up coupling one pair at a time always overstates the worst case by at least a stated minimum.
Who did this. The lab’s AI agents did the research and engineering. Nick Harris, founder. CTO of VivaMed BioPharma; co-founder of MedSim.ai, FastRead.io and Formulai. The lab’s track record.
What we showed
Adding up coupling one pair at a time does this for every layout in one narrow family, inside the lab’s simplified physics model. The computer search covered the whole family, not a sample. Inside that simplified model it guarantees a minimum size for the overstatement; the limit line below says what happens against the lab’s more exact solver.
Adding up coupling pair by pair overstates the worst coupling by at least 1.10467× (at least 10.467%), rounded down from the certified value.
- Limit.
- A simplified model the lab froze, not a full field solve, and one narrow family of layouts. Against the lab’s more exact solver the over-estimate is smaller (about 9.8 percent) and was measured on examples only, not proved.
The problem
The lab’s starting point is that fast chip-package tools estimate the coupling within a group of vertical wires by adding it up one pair at a time; its record gives no source for which commercial tools do. In the sources the lab searched (listed below), how wrong that pair-by-pair sum can be appears only as sampled examples, not as a guaranteed minimum over a whole family of layouts.
What it means for a buyer
If you build or use fast extraction tools: in the sources the lab searched, the pair-by-pair sum appears only with sampled examples of how wrong it can be. This computer search covers every point of one family of four-connection layouts and gives a guaranteed minimum over-estimate in that model, not a sample. A too-high estimate errs on the cautious side, and our record does not say what it costs a package designer.
Who we expect would buy
Teams we expect would care (no customer or pilot yet): makers of fast chip-package and interposer extraction tools (electronic design automation vendors) and package signal-integrity teams that use such tools.
Why now
Chiplet packages are going vertical: the UCIe chiplet-interconnect standard now covers stacked, three-dimensional packaging, with bonded connections spaced as little as a micron apart (report). The closer those vertical connections sit, the more a package team depends on a coupling model its reviewers can trust.
Why you can trust the check
The lab’s check re-runs the whole search, and it failed as it should when the stored minimum was made tighter. The model, the search and the check are all the lab’s own; no outside tool grades this.
No outside firm has audited it. How this result’s check works, step by step.
What this does not show yet
- It holds inside a simplified physics model the lab froze, not a full field solve, for one narrow family of layouts whose sizes and spacings are held inside a fixed range.
- Against the lab’s more exact solver the over-estimate is smaller (about 9.8 percent) and was measured on examples only, not proved.
- It says nothing about fabricated or measured silicon, and nothing about what an over-estimate of this size costs a package designer or whether it matters for sign-off.
- The claim assumes that fast extraction tools add up coupling pair by pair. The lab’s own record notes that no source is given for which commercial tools do.
- One paper in the lab’s prior-art list treats pairwise against many-body electrostatics rigorously, for a different shape (dielectric spheres).
Prior work
Named in the lab’s prior-art search for this result, and credited here.
- TSV-Based 3-D ICs: Design Methods and Tools, Tiantao Lu, Caleb Serafy, Zhiyuan Yang, Sandeep Kumar Samal, Sung Kyu Lim, Ankur Srivastava, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 36(10), 2017
- Rigorous treatment of pairwise and many-body electrostatic interactions among dielectric spheres at the Debye–Hückel level, O. I. Obolensky, T. P. Doerr, Yi-Kuo Yu, European Physical Journal E, 2021
- Interval Computations: Introduction, Uses, and Resources, R. B. Kearfott, preprint hosted by reliable-computing.org (year not printed on the fetched copy)
The exact wording, for a technical reader
The lab’s own sentences and figures for this result, word for word, its limits in plain words where the lab’s text cannot be reprinted and its formal statement: Pair-by-pair coupling estimates overstate the worst case, in a model, exact wording. The formal statements of all the results are on one page.
Check it yourself
- This result’s file: every sentence and figure on this page that is the lab’s own, copied from its current record at the commit the file names.
- The lab’s result file, copied from its codebase at the commit it names.
- The file this result’s statement is checked against (a proof, a certificate or a measurement record; the formal statements page says which).
- The formal statement, set as a formula.
- interval-core (open source): Validated interval arithmetic with directed outward rounding.
- ChipletOS, the company that carries this result.
Related results across the group
- This result on chipletos.com, ChipletOS’s own site.
- A fast coupling model, graded by outside solvers (ChipletOS, chip packaging)
- Checked brightness ranges for chip prints (ChipletOS, chip printing)
- The capacitance flat models leave out (ChipletOS, chip packaging)
- Signing off some tiles near a chip-mask edit, in simulation (ChipletOS, chip printing)
- A near-constant-size sign-off record for a photomask (ChipletOS, chip printing)