· VerifyCore Labs
The capacitance flat chip-package models leave out
A flat, two-dimensional model treats each vertical connection in a chip package as an endless cross-section. Three results on what that leaves out.
Who did this. The lab’s AI agents did the research and engineering. Nick Harris, founder. CTO of VivaMed BioPharma; co-founder of MedSim.ai, FastRead.io and Formulai. The lab’s track record.
Every chip package is threaded with vertical metal connections that carry signals and power between layers. One fast way to model them is in two dimensions: a slice through the connection, assumed to go on forever. That assumption is what makes such a model fast. This post is about three results from our lab on what it costs, and on how to grade a fast model against software it did not write.
What a flat model cannot see
A real connection is finite. It has two ends, and charge gathers there. A model that treats the connection as an endless flat slice leaves that charge out by construction, not by poor tuning. The lab’s record states the problem plainly:
A package model that treats each vertical connection as an infinitely long two-dimensional cross-section leaves out the capacitance at its ends
To measure how much is missing, our agents built a three-dimensional electrical solver of the lab’s own and, before trusting it, checked it against shapes whose answers are known exactly. Then they used it on a single simplified connection. In the lab’s own plain words:
The lab built its own three-dimensional electrical solver, checked it first against textbook shapes whose answers are known exactly … about 40% of its charge-storing capacity (capacitance) sits at its two ends, a share that the lab's flat, two-dimensional models leave out by design
That share is measured with the connection driven as one of a pair, for one bare cylinder at one size.
Checked against an outside solver
A solver checked only against itself shows little. The lab cross-checked its own against FastCap, an established outside three-dimensional solver, which it ran on its own mesh of the shape; the lab’s own wording is on the result page. The two solvers differ by about as much as FastCap’s own answer changes when its mesh (the grid of small patches the shape is split into) is made finer. So the mesh alone could explain the difference, and closer agreement than that cannot be claimed.
The limit matters as much as the number. The measurement is for one simplified connection, a bare cylinder at one standard size, without the pads and metal planes a real package connection ends in. That flat models miss the ends is well known; whether the missing share changes any figure the lab’s own models sign off on has not been tested.
The pair-by-pair sum
The lab’s starting point is a second simplification it says fast tools make: to estimate how strongly a group of connections couple, they add up the coupling one pair at a time (its record gives no source for which commercial tools do). For one narrow family of layouts, four connections held within fixed size and spacing ranges, the lab’s computer search covered every point of the family inside a simplified physics model it froze, not a sample, and found that the pair-by-pair sum always overstates the worst coupling in that model:
Adding up coupling pair by pair overstates the worst coupling by at least 1.10467× (at least 10.467%), rounded down from the certified value.
That rounded-down figure is a guaranteed minimum over the whole family, in that model. Against the lab’s more exact solver the over-estimate is smaller, just under ten percent, and it is measured on examples rather than proved.
Graded by software we did not write
The third result answers the question a buyer’s reviewer asks first: who graded the model? The lab checked its fast predictor of coupling against two outside field solvers. FastCap graded every sampled set of layouts and Palace graded one slice of them only; on those, the predictor came closer than the lab’s own pair-by-pair sum, a baseline the lab defined. The record states it in its own terms, where the “many-body operator” is the lab’s predictor and “pairwise superposition” is that pair-by-pair sum:
the many-body operator beats pairwise superposition on every sampled population measured
It covers capacitance only, the charge-storage part of the coupling, and only the predictor’s mutual-coupling numbers; inductance still comes from the lab’s own two-dimensional solver. The two outside solvers also disagree with each other about absolute accuracy, and most of that disagreement is explained by reasoning rather than measured.
Why now
Chiplet packages are going vertical: the UCIe chiplet-interconnect standard now covers stacked, three-dimensional packaging, with bonded connections spaced as little as a micron apart (report). The closer those vertical connections sit, the more a package team depends on a coupling model its reviewers can trust, and on knowing what a flat model leaves out.
Who this is for
Chip-package and interposer design teams, and the extraction-tool vendors that serve them. For a vendor, the useful part is not a claim that fast models are wrong. It is a way to size what they leave out, a guaranteed minimum, in a simplified model, for the pair-by-pair sum’s error across a whole family of layouts, and a grading method that uses outside solver programs, which a buyer could repeat on their own installation of those programs; the lab’s own code, which the grading also needs, is not public.
What we do not claim
- The end-effect share is measured for one simplified connection, not a real package connection with pads and planes.
- The pair-by-pair floor holds inside a simplified model the lab froze, for one narrow family of layouts.
- The outside-solver check covers capacitance only, and most of the outside solvers’ disagreement is explained by reasoning rather than measured.
- None of this is a measurement of fabricated silicon.
The capacitance flat models leave out: the full result
Pair-by-pair coupling estimates overstate the worst case, in a model: the full result
A fast coupling model, graded by outside solvers: the full result
On chipletos.com: Why a flat model of a via misses its ends
On chipletos.com: What an independent-solver check shows and does not show