ChipletOS · Chip packaging
A fast coupling model, graded by outside solvers
On every sample set FastCap graded, and on the one slice of layouts Palace graded, the lab’s fast model of how electrical signals couple between the vertical wires of a chip package came closer to those two outside physics programs than the lab’s own pair-by-pair sum did, for one property, the charge they can store (capacitance). That sum is a baseline the lab defined, and the lab’s own records say full-wave field solvers do not use it.
Who did this. The lab’s AI agents did the research and engineering. Nick Harris, founder. CTO of VivaMed BioPharma; co-founder of MedSim.ai, FastRead.io and Formulai. The lab’s track record.
What we showed
FastCap graded the sample sets and Palace graded one slice of layouts only. On every sample set measured, the lab’s fast model came closer to them than the lab’s own pair-by-pair sum did.
- Limit.
- Capacitance only; inductance still comes from the lab’s own solver. The two outside programs do not agree with each other about how accurate the lab’s own solver is, and most of that disagreement is explained by reasoning, not measured.
The problem
Chip-package design tools need a fast estimate of how strongly neighbouring vertical wires affect each other. If the only grader of that estimate is software written by the same lab, a buyer’s reviewer cannot treat its accuracy figures as independent.
What it means for a buyer
If you buy or build fast extraction tools: accuracy graded only by a vendor’s own software is not independent. Here two outside programs served as graders: FastCap graded the sample sets and Palace one slice of layouts only, and on them the lab’s fast model came closer than the lab’s own pair-by-pair sum did. What this gives a buyer today is a fast model checked against outside programs for one property; it does not yet give a reliable size for the improvement.
Who we expect would buy
Teams we expect would care (no customer or pilot yet): makers of fast chip-package and interposer extraction tools (electronic design automation vendors) and package signal-integrity teams.
Why now
Chiplet packages are going vertical: the UCIe chiplet-interconnect standard now covers stacked, three-dimensional packaging, with bonded connections spaced as little as a micron apart (report). The closer those vertical connections sit, the more a package team depends on a coupling model its reviewers can trust.
Why you can trust the check
The graders, FastCap and Palace, are programs the lab did not write; the lab ran them itself, against a baseline it defined, so a buyer would want to repeat the grading on their own installation of both programs.
No outside firm has audited it. How this result’s check works, step by step.
What this does not show yet
- It covers capacitance only, and only the model’s coupling numbers between different wires. Inductance still comes from the lab’s own two-dimensional solver, because the outside tool for it returns an unusable answer on the multi-wire case.
- The Palace check covers a single coupling-heavy slice of layouts, with most of its points left out.
- The two outside programs give different answers for how accurate the lab’s own solver is, and most of that difference is explained by reasoning rather than measured. The lab’s own record puts it this way: “Only 19.2% of the log gap is measured”. The “log gap” is the size of the difference between the two programs’ answers, expressed as a ratio, so this says that only part of the difference has been measured.
- The lab’s own record holds several different figures for how much closer the fast model came to FastCap, so this site prints no size for the improvement.
- What it beats is the lab’s own pair-by-pair sum, a baseline the lab defined; the lab’s own records say full-wave field solvers do not use that sum.
Prior work
Named in the lab’s prior-art search for this result, and credited here.
- IEEE 1597.1-2008, IEEE Standard for Validation of Computational Electromagnetics Computer Modeling and Simulations, IEEE Standards Association, 2008
- CNN-Cap: Effective Convolutional Neural Network Based Capacitance Models for Full-Chip Parasitic Extraction, Dingcheng Yang, Wenjian Yu, Yuanbo Guo, Wenjie Liang, arXiv 2107.06511, 2021
- FastCap: a Multipole Accelerated 3-D Capacitance Extraction Program, Keith Nabors, Jacob K. White, IEEE TCAD 10(11), 1991 (IEEE CEDA page)
- Palace documentation (Home), AWS Labs, 2026
The exact wording, for a technical reader
The lab’s own sentences and figures for this result, word for word, its limits in plain words where the lab’s text cannot be reprinted: A fast coupling model, graded by outside solvers, exact wording.
Check it yourself
- This result’s file: every sentence and figure on this page that is the lab’s own, copied from its current record at the commit the file names.
- The lab’s result file, copied from its codebase at the commit it names.
- ChipletOS, the company that carries this result.
Related results across the group
- This result on chipletos.com, ChipletOS’s own site.
- Checked brightness ranges for chip prints (ChipletOS, chip printing)
- The capacitance flat models leave out (ChipletOS, chip packaging)
- Pair-by-pair coupling estimates overstate the worst case, in a model (ChipletOS, chip packaging)
- Signing off some tiles near a chip-mask edit, in simulation (ChipletOS, chip printing)
- A near-constant-size sign-off record for a photomask (ChipletOS, chip printing)