ChipletOS · Chip printing

Signing off some tiles near a chip-mask edit, in simulation

A method that signs off, in the lab’s own simulator, a small piece of a chip-mask design (a tile) next to a small edit as still valid without recomputing it. It applies when a bound the lab computes on the edit’s effect fits inside the tile’s safety margin; this site does not name what checks that bound.

Who did this. The lab’s AI agents did the research and engineering. Nick Harris, founder. CTO of VivaMed BioPharma; co-founder of MedSim.ai, FastRead.io and Formulai. The lab’s track record.

The problem

After a small change to a chip-mask design, the affected tiles are normally fully re-simulated and re-checked, which is slow at full-chip scale. The lab’s own tests show this method does not yet relieve that much: on its test edits it saved only a small share of the recomputation.

What it means for a buyer

If you sell mask-correction or verification software: fully re-simulating every affected tile after every change is the slow step at full-chip scale. This method signs a changed tile off when a bound the lab computes on the edit’s effect fits inside the safety margin the tile already had. On the lab’s test edits it has so far spared only a small share of the recomputation.

Who we expect would buy

Teams we expect would care (no customer or pilot yet): mask-synthesis and physical-verification software vendors (mask correction and mask-data preparation).

Why now

Simulating how masks will print already costs the industry tens of billions of processor hours a year, by NVIDIA’s account when it launched its GPU lithography library with ASML, TSMC and Synopsys (press release). A check that could sign a mask off faster than a full re-simulation would cut into that bill; the lab has not measured any such saving for its own checks.

Why you can trust the check

The lab’s check confirms that the evidence file is unchanged and still carries the claimed figure; the point-by-point comparison itself is redone by a longer command in the lab’s code, which this site does not run. Everything is relative to the lab’s simulator, so a buyer would want to re-run it on their own masks.

No outside firm has audited it. How this result’s check works, step by step.

What this does not show yet

• The sign-off applies only when the edit’s computed effect fits inside a tile’s margin, and on the lab’s test edits that spared only a small share of the recomputation (the figure is in the limit line above).
• This site does not name what checks the bound on an edit’s effect, and the bound relies on the edit’s declared reach (its “declared halo”) being right, as the chain test below shows.
• It is shown for single, isolated edits in the lab’s own simulator, not on silicon.
• The lab also tried a chain of four edits in a row. It set the “declared halo” (how far an edit is declared to reach) to zero on purpose, a setting it stamps “not a certificate”. Then it let through 9 of 64 tile checks that came out worse than a full recomputation, by up to 4.3267 nm (nanometres). Declared honestly, the same chain let none through. Soundness over chains of edits in general is not established.
• Grey or partial edits, and other masks, are not covered.
• The lab’s own record also says that beyond the point where the mask stops printing correctly (its “printability cliff”), the method costs more time than recomputing.

Prior work

Named in the lab’s prior-art search for this result, and credited here.

• Incremental Verification of Neural Networks, Shubham Ugare, Debangshu Banerjee, Sasa Misailovic, Gagandeep Singh, PLDI 2023 (arXiv 2304.01874)
• Shared Certificates for Neural Network Verification, Marc Fischer, Christian Sprecher, Dimitar I. Dimitrov, Gagandeep Singh, Martin Vechev, CAV 2022 (arXiv 2109.00542)

The exact wording, for a technical reader

The lab’s own sentences and figures for this result, word for word, its limits in plain words where the lab’s text cannot be reprinted: Signing off some tiles near a chip-mask edit, in simulation, exact wording.

Check it yourself

• This result’s file: every sentence and figure on this page that is the lab’s own, copied from its current record at the commit the file names.
• The lab’s result file, copied from its codebase at the commit it names.
• ChipletOS, the company that carries this result.

Related results across the group

• This result on chipletos.com, ChipletOS’s own site.
• A fast coupling model, graded by outside solvers (ChipletOS, chip packaging)
• Checked brightness ranges for chip prints (ChipletOS, chip printing)
• The capacitance flat models leave out (ChipletOS, chip packaging)
• Pair-by-pair coupling estimates overstate the worst case, in a model (ChipletOS, chip packaging)
• A near-constant-size sign-off record for a photomask (ChipletOS, chip printing)

On the blog

• Sparing re-simulation of some tiles near a chip-mask edit
• Ten results, and who they are for

All resultsContact / M&A